WLAN trigger frame padding for meeting minimum processing time requirement of receiver

ABSTRACT

A WLAN Access Point (AP) includes a MAC processor and a PHY processor. The MAC processor is configured to generate a trigger frame including user information fields destined to respective STAs, and a padding field including one or more padding bits, to determine a number of padding bits that, after the trigger frame including the padding bats being encoded for transmission, satisfy a processing-time constraint imposed by the STAs, and to insert the determined number of padding bits in the padding field. The PHY processor is configured to generate a packet from the trigger frame, including encoding the trigger frame in accordance with an ECC, into one or more code words whose length depends on a number of padding bits in the padding field, to generate multiple modulated symbols from the one or more code words of the packet, and to transmit the modulated symbols to the STAs.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication 62/769,351, filed Nov. 19, 2018, whose disclosure isincorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to wireless communication, andparticularly to methods and systems for padding a Trigger frame formeeting minimum processing time requirement of the receiver.

BACKGROUND

Some Wireless Local-Area Network (WLAN) communication systems supportmulti-user schemes for communicating with multiple users simultaneously.A simultaneous uplink transmission from multiple client stations may beinitiated by an Access Point (AP) sending to these client stations asuitable Trigger frame. The Trigger frame should be processed by therecipient receivers so that the client stations can respond with asimultaneous uplink transmission. The AP should control the length ofthe Trigger frame to allow sufficient processing time at the receiversof the client stations. Uplink multi-user operation in WLANs isspecified, for example, in a draft IEEE 802.11ax standard, entitled“P802.11ax™/D3.3—IEEE Draft Standard for InformationTechnology—Telecommunications and Information Exchange Between SystemsLocal and Metropolitan Area Networks—Specific Requirements Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY)Specifications, Amendment Enhancements for High Efficiency WLAN,” 2018,which is incorporated herein by reference.

The description above is presented as general overview of related art inthis field and should not be construed as an admission that any of theinformation it contains constitutes prior art against the present patentapplication.

SUMMARY

An embodiment that is described herein provides a Wireless Local-AreaNetwork (WLAN) Access Point (AP), including a Medium Access Control(MAC) processor and a physical layer (PHY) processor. The MAC processoris configured to generate a trigger frame including at least (i) one ormore user information fields destined to one or more respective WLANclient stations (STAs), and (ii) a padding field including one or morepadding bits, to determine a number of padding bits required that, afterbeing inserted into the padding field and the trigger frame beingencoded for transmission, satisfy a processing-time constraint imposedby the STAs, and to insert the determined number of padding bitsrequired in the padding field. The physical layer (PHY) processor isconfigured to generate a packet from the trigger frame, includingencoding the trigger frame containing the padding field in accordancewith an Error Correction Code (ECC), into one or more Code Words (CWs)having a CW length that depends on a number of padding bits in thepadding field, to generate multiple modulated symbols from the one ormore CWs of the packet, and to transmit the modulated symbols to theSTAs.

In some embodiments, the MAC processor is configured to receive, beforegenerating the trigger frame, multiple processing-time constraint valuesfrom one or more respective STAs that participate in a simultaneousuplink transmission to be triggered by the trigger frame, and todetermine the number of padding bits required based on a longest valueamong the multiple received processing-time constraint values. In otherembodiments, the MAC processor configured to adjust one or more of thereceived processing-time constraint values, before selecting the longestvalue, based on respective locations of the user information fields ofthe STAs in the Trigger frame.

In an embodiment, the PHY processor is configured to encode the triggerframe with the ECC applying a Binary Convolutional Code (BCC). Inanother embodiment, the MAC processor is configured to determine thenumber of padding bits required, by calculating a partial number ofpadding bits required for reaching a far boundary of a symbol to which alast BCC encoded bit of a last user information field is mapped. In yetanother embodiment, the PHY processor is configured to encode thetrigger frame with the ECC applying a Low-Density Parity-Check (LDPC)code. In yet further another embodiment, the MAC processor is configuredto determine the number of padding bits required, by calculating apartial number of padding bits required for reaching a far boundary of asymbol to which a last encoded bit of a LDPC code word that encodes alast bit of a last user information field, is mapped.

In some embodiments, the MAC processor is configured to determine thenumber of padding bits required, by evaluating an expected modificationto an encoding scheme applied using the ECC caused by adding the paddingbits, the modification changes a length of the trigger frame. In otherembodiments, the processing-time constraint is indicative of anadditional processing time required by a STA, and the MAC processor isconfigured to determine a partial number of the padding bits required,independently of the processing-time constraint.

In an embodiment, the MAC processor is configured to determine thenumber of padding bits required using an iterative process thatiteratively increases the number of padding bits required until theprocessing-time constraint is met. In another embodiment, the APsupports a Space-Time Block Coding (STBC) mode of operation, and the MACprocessor is configured to determine the number of padding bits requireddepending on the STBC mode.

There is additionally provided, in accordance with an embodiment that isdescribed herein, a method for communication, including, in a WirelessLocal-Area Network (WLAN) Access Point (AP) that includes a MediumAccess Control (MAC) processor, and a physical layer (PHY) processor,generating by the MAC processor a trigger frame including at least (i)one or more user information fields destined to one or more respectiveWLAN client stations (STAs) and (ii) a padding field including one ormore padding bits. A number of padding bits required that, after beinginserted into the padding field and the trigger frame being encoded fortransmission, satisfy a processing-time constraint imposed by the STAB,is determined by the MAC processor and the determined number of paddingbits required is inserted in the padding field. A packet is generatedfrom the trigger frame, by the PHY processor, including encoding thetrigger frame containing the padding field in accordance with an ErrorCorrection Code (ECC), into one or more Code Words (CWs) having a CWlength that depends on a number of padding bits in the padding fieldmultiple modulated symbols are generated by the PHY processor from theone or more CWs of the packet, and the modulated symbols are transmittedto the STAB.

The present disclosure will be more fully understood from the followingdetailed description of the embodiments thereof, taken together with thedrawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a wirelesscommunication system in which an Access Point (AP) pads a Trigger framethat triggers simultaneous uplink transmissions by multiple clientstations (STAs), for meeting a processing-time constraint of the clientstations (STAs), in accordance with an embodiment that is describedherein;

FIGS. 2A and 2B are diagrams that schematically illustrate a partialpacket comprising a Trigger frame, and corresponding encoded its andOFDM symbols resulting from encoding the partial packet using a BinaryConvolutional Code (BCC) or a Low-Density Parity-Check (LDPC) encodingscheme;

FIG. 3 is a flow chart that schematically illustrates method for paddinga Trigger frame for meeting a processing-time constraint, in accordancewith an embodiment that is described herein; and

FIG. 4 is a flow chart that schematically illustrate a method foriteratively determining the padding length required in a Trigger framefor meeting a processing-time constraint, in accordance with anembodiment that is described herein.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments that are described herein provide methods and systems forpadding a Trigger frame destined to multiple receivers, by determiningthe number of padding bits required in the Trigger frame for meetingminimum processing time requirement of the receiver. The Trigger framemay be broadcasted by a transmitter of a Wireless LAN (WLAN) device forinitiating simultaneous uplink transmissions by client stations.Determining the number of padding bits in the Trigger frame is based ontime duration reported by each client station, required by that clientstation for processing the Trigger frame. The Trigger frame length maybe controlled by properly selecting the number of padding bits. When thenumber of padding bits is too small, a simultaneous uplink transmissionmay fail because at least one of the client stations receiving theTrigger frame will not be ready on time. On the other hand, using alarger than necessary number of padding bits reduces bandwidth usageefficiency.

In some WLAN communication systems, an Access Point (AP) communicateswith one or more WLAN client stations (STAs). The transmission directionfrom the AP toward the STAs is referred to as Downlink (DL), whereas thetransmission direction from the STAs toward the AP is referred to asUplink (UL). The IEEE 802.11ax standard cited above, specifies DL and ULtransmissions using Orthogonal Frequency-Division Multiple Access(OFDMA) techniques in which subsets of subcarriers, referred to asResource Units (RUs) are allocated for the transmissions.

The IEEE 802.11ax standard supports coordinated UL transmissions frommultiple STAs, initiated by the AP broadcasting a special type of packetcontaining a Trigger frame. The Trigger frame includes information thatthe STAs need for generating the response UL transmissions, such asduration of the UL packets, RU allocation, modulation method, payloadlength, and the like.

Each of the STAs receiving the Trigger frame process the Trigger frameto extract the information it needs for generating the UL responsetransmission. Since the STAs may have different processing and storagecapabilities, different STAs may require different time-durations forprocessing the Trigger frame and generating a response packet.

In some embodiments, before broadcasting the Trigger frame, the APreceives from multiple STAs that participate in a simultaneous ULtransmission, respective processing-time requirements, from which the APderives a common processing-time constraint, e.g., based on the longesttime requirement reported by the STAs. By inserting one or more paddingbits in the Trigger frame, the transmission duration of the Triggerframe increases, which allows longer processing time for the STAs. Forefficient usage of the communication link, however, it is desirable toadd the smallest number of padding bits that still satisfies theprocessing-time constraint.

Determining the number of padding bits required is not trivial. TheTrigger frame is typically encoded in accordance with an ErrorCorrection Code (ECC) into one or more Code Words (CWs). Adding paddingbits to the Trigger frame may, however, result in modifying the ECCencoding scheme applied to the Trigger frame including the padding bits,which may result in violating the processing-time constraint. Forexample, the encoding scheme may depend on padding when the code wordlength depends on the frame length and therefore also on the number ofpadding bits added. As another example, the number of padding bits mayaffect a puncturing and/or shortening scheme applied as part of theencoding scheme.

In some embodiments, the AP comprises a Medium Access Control (MAC)processor, and a Physical Layer (PHY) processor. The MAC processorgenerates a Trigger frame comprising at least (i) one or more userinformation fields destined to one or more respective STAs and (ii) apadding field comprising one or more padding bits. The MAC processordetermines the number of padding bits required that, after beinginserted into the padding field and the trigger frame being encoded fortransmission using an ECC, satisfy the processing-time constraintimposed by the STAs. The MAC processor inserts the determined number ofpadding bits required in the padding field. The PHY processor generatesa packet from the Trigger frame, including encoding the trigger framecontaining the padding field in accordance with the underlying ECC. ThePHY processor generates multiple modulated symbols from the one or moreCWs of the packet and transmits the modulated symbols to the STAs.

In some embodiments, before generating the Trigger frame for triggeringsimultaneous UL transmissions by client stations, the MAC processorreceives multiple processing-time constraint values from one or morerespective STAs and determines the number of padding bits required basedon a longest processing-time constraint value among the multiplereceived processing-time constraint values.

In some embodiments, the PHY processor is configured to encode theTrigger frame with a Binary Convolutional Code (BCC). In suchembodiments, the MAC processor determines the number of padding bitsrequired, by calculating a partial number of padding bits required forreaching a far boundary of a symbol to which a last BCC encoded bit of alast user information field is mapped.

In other embodiments, the PHY processor is configured to encode theTrigger frame with a Low-Density Parity-Check (LDPC) code. In theseembodiments, the MAC processor determines the number of padding bitsrequired, by calculating a partial number of padding bits required forreaching a far boundary of a symbol to which a last encoded bit of aLDPC code word that encodes a last bit of a last user information field,is mapped.

In an embodiment, the MAC processor determines the number of paddingbits required, by evaluating an expected modification to an encodingscheme applied using the ECC, e.g., due to omitting from transmissionone or more encoded bits in the one or more CWs. Omitting encoded bitsmay result, for example, by applying to the encoded bits puncturing,shortening or both.

In some embodiments, the processing-time constraint is indicative of anadditional processing time required by a STA, and the MAC processordetermines a partial number of the padding bits required, independentlyof the processing-time constraint. The partial number of padding bitsmay be required for reaching a certain symbol, e.g., as described above.In some embodiments, the MAC processor determines the number of paddingbits required using an iterative process that iteratively increases thenumber of padding bits required until the processing-time constraint ismet. The number of padding bits added may be the same or differentacross the iterations.

In some embodiments, the AP supports a Space-Time Block Coding (STBC)mode of operation, in which the AP transmits multiple copies of a datastream via multiple antennas. In such embodiments, the MAC processor maydetermine the number of padding bits required, depending on whether theAP operates in the STBC mode.

In the disclosed techniques, padding bits are added to a Trigger framefor meeting processing-time constraints imposed by client STAs. TheTrigger frame is destined to multiple client stations that in responseto the Trigger frame transmit simultaneous UL transmissions. Severalmethods for calculating a number of padding bits sufficient for meetingthe constraint are described. Some closed techniques take intoconsideration, directly or indirectly, possible modification to theencoding scheme applied due to the added bits. The different methods mayresult in different accuracy in evaluating the minimum number of paddingbits required.

FIG. 1 is a block diagram that schematically illustrates a wirelesscommunication system 20 in which an Access Point (AP) 24 pads a Triggerframe that triggers simultaneous uplink transmissions by multiple clientstations (STAs) 28, for meeting a processing-time constraint of theclient stations (STAs), in accordance with an embodiment that isdescribed herein.

Communication system 20 comprises, in an example embodiment, aWireless—Local Area Network (WLAN) communication system operating inaccordance with the IEEE 802.11 family of standards, such as, forexample, the IEEE 802.11ax standard cited above.

AP 24 comprises a Base Band (BB) processor 30, which comprises a MACprocessor 32 and a PRY processor 36. Each of MAC processor 32 and PRYprocessor 36 comprises various elements, as will be described below. Inthe description that follows, MAC processor 32 is also referred toherein as a “MAC module,” and PHY processor 36 is also referred toherein as a “PHY module.” AP 24 further comprises a Radio-FrequencyFront-End (RE-FE) 40 coupled to one or more antennas 42. In someembodiments, AP 24 processes data in a layered scheme in which MACprocessing is followed by PHY processing in the downlink direction, andPHY processing is followed by MAC processing in the uplink direction.MAC module 32 and PHY module 36 are also referred to herein as a “MACprocessor” and a “PHY processor,” respectively.

In the description that follows, data units processed at the MAC layerare referred to as “frames” whereas data units processed at the PHYlater are referred to as “packets.” In the IEEE 802.11 family ofstandards, a frame processed at the MAC layer, e.g., using MAC module32, is referred to as a MAC Protocol Data Unit (MPDU). A packetprocessed at the PHY layer, e.g., by PHY module 36, is referred to as aPLCP Protocol Data Unit (PPDU). The PLCP refers to as a Physical LayerConvergence Procedure (PLCP) sublayer of the PHY layer. The PLPCsublayer handles data in the form of a PLCP Service Data Unit (PSDU),which is equivalent to the MPDU, and generates a PPDU by appending apreamble and PHY header information to the PSDU. The preamble typicallyis used for synchronization and channel estimation at the receiver. Thepreamble also contains information required for processing the packet,such as the Modulation and Coding Scheme (MCS) used, the number Nss ofspatial streams, Bandwidth information and the like.

In communication system 20, AP 24 communicates wirelessly with one ormore STAs 28 in its vicinity. In some embodiments, e.g., as specified inthe IEEE 802.11ax standard, AP 24 initiates simultaneous uplinktransmissions by multiple STAs 28, by broadcasting a DL Trigger frame 44in the downlink direction. AP 24 typically transmits DL Trigger frame 44within a downlink PPDU (not shown). In response to receiving the DLTrigger frame, STAs 28 that participate in the UL transmission transmitrespective uplink PPDUs 48, simultaneously. DL Trigger frame 44 carriesinformation that the STAs use for generating uplink PPDUs 48, as will bedescribed below.

In some embodiments, MAC module 32 comprises a trigger frame constructor50 that generates a MAC Trigger frame 52. Note that DL Trigger frame 52is the transmitted version of MAC Trigger frame 52. In the example ofFIG. 1, trigger frame constructor 50 generates MAC Trigger frame 52 inaccordance with a trigger frame format specified in the IEEE 802.11axstandard. In some embodiments, trigger frame constructor 50 supportsgenerating various types of frames, at the MAC layer.

MAC module 32 provides Trigger frame 52 to PRY module 36, whichcomprises an Error Correction (ECC) module 56 and an OrthogonalFrequency-Division Multiplexing (OFDM) module 58. In some embodiments,ECC module 56 supports multiple selectable ECC schemes. In the exampleof FIG. 1, FCC module 56 supports a Binary Convolutional Code scheme anda Low-Density Parity-Check (LDPC) coding scheme. Alternatively, anyother suitable ECC scheme can also be used. BCC and LDPC schemes thatare applicable in PHY module 36 are specified, for example, in the IEEE802.11ax standard. The actual ECC scheme employed typically depends onvarious parameters such as the number of payload bits to be encoded, thetransmission data rate, a modulation scheme used and the like.

In the downlink direction, PHY module 36 receives MAC frames, e.g., suchas MAC Trigger frame 52, from MAC module 32 for processing. The PHYmodule typically appends information to the MAC layer frame to produce apacket that includes headers and a payload part. The ECC module 56encodes the packet payload (the payload part comprises, for example, MACTrigger frame 52) in accordance with the underlying ECC scheme selected.OFDM module 58 receives a packet with an encoded payload and maps thepacket bits into a sequence of OFDM symbols. In some embodiments, theOFDM module first maps the packet bits into respective points in apredefined constellation, e.g., a Quadrature Amplitude Modulation (QAM)constellation, and then maps the constellation points into the OFDMsymbols. In the present context, mapping between bits and symbols isalso referred to as a “modulation” operation. In an embodiment, OFDMmodule 58 further converts the OFDM symbols to an analog signal using aDigital to Analog Converter (DAC) (not shown). RF-FE 40 up-converts theanalog signal to a desired RF band and transmits the up-converted signalvia one or more antennas 42.

In the uplink direction, RF-FE 40 receives RF signals, via antennas 42,from one or more STAs 28. The RF signals may carry, for example, PPDUs48, encoded by the STA using an ECC that is decodable by ECC module 56.RF-FE 40 down-converts a received RF signal to baseband (or to someintermediate frequency) and converts the down-converted signal intodigital form using an Analog to Digital Converter (ADC) (not shown).OFDM module 58 demodulates OFDM symbols carried to the down-convertedsignal to recover the encoded PPDUs. ECC module 56 decodes the ECC ofthe encoded PPDUs to recover the PPDUs data, which PHY module 36provides to MAC module 32.

The MAC and PHY downlink and uplink processing described above have beensimplified to include only tasks required for understanding thedisclosed techniques, for the sake of clarity. In practice, the MACmodule and the PHY module may apply various additional processing, taskssuch as scrambling, interleaving, post-encoding padding and the like.

In some embodiments, MAC module 32 further comprises a processing-timeconstraint 60 and a MAC padding module 64. Processing-time constraint 60holds a value (e.g., in a memory or register, not shown) that isindicative of the processing time required by the client STAs forprocessing DL Trigger frame 44. In some embodiments, before broadcastinga given Trigger frame (e.g., DL Trigger frame 44), AP 24 receives fromSTAs 28 that participate in the upcoming simultaneous transmission,respective processing-time durations of these STAs. In an embodiment, toallow sufficient processing time at all participating STAs, MAC module32 calculates the value of processing-time constraint 60 as the longestduration among the multiple processing time durations reported.

Based on processing-time constraint 60, MAC padding module determinesthe number of padding bits required for meeting the processing timerequirement. Trigger frame constructor 50 inserts into a Padding field66 of the MAC Trigger frame, the number of padding bits determined byMAC padding module 64. A MAC Trigger frame 52 constructed as describedabove and broadcasted as DL Trigger frame 44, is padded with a number ofpadding bits that allow sufficient processing time of the Trigger frameby each of the participating STAs, so that the STAs respond with asimultaneous UL transmission.

MAC Trigger frame 52 may be formatted in various ways. In the example ofFIG. 1, MAC Trigger frame 52 is formatted in accordance with the IEEE802.11ax specifications, in which the MAC Trigger frame comprises a MACheader comprising a Frame Control field, a Duration field, as well as RAand TA fields specifying addressing information. MAC Trigger frame 52further comprises a Common Info field, one or more User Info fields 62,Padding field 66, and a Frame Check Sequence (FCS) field that serves asan error detection code. The MAC module calculates the value of the FCSfield, e.g., by calculating a suitable Cyclic Redundancy Check (CRC)code over selected preceding fields of MAC Trigger frame 52. Forexample, the CRC calculation typically excludes the SERVICE bits field,which is added later by the PHY module.

The Common Info field comprises information addressed to all clientSTAs, such as the length (in microseconds) of uplink PPDUs 48, thebandwidth to be used for transmitting uplink PPDUs 48 and the like. EachUser Info field 62 comprises information addressed to a specific STA,such as, RU allocation for that STA, ECC scheme used such as BCC orLDPC, and a Modulation and Coding Scheme (MCS). Padding field 66contains one or more padding bits as calculated by MAC padding module64. Alternatively, in case of zero padding, the Padding field may beomitted from MAC Trigger frame 52.

Note that by adding the padding bits, the transmission time of the MACTrigger frame part following the User Info fields increase, which allowsthe client STAs more time for processing the DL Trigger frame andgenerating the uplink response PPDUs. Methods for determining the numberof padding bits required for meeting processing-time constraint, will bedescribed in detail below.

The format of MAC Trigger frame 52 in FIG. 1, which is based on the IEEE802.11ax standard, is given by way of example, and other suitableformats for the MAC Trigger frame can also be used. In describing theformat of MAC Trigger frame 52, details that are not relevant forunderstanding the disclosed techniques have been omitted for clarity.

The partition of tasks between the MAC and PHY modules is given by wayof example. In alternative embodiments, other partitioning of tasks canalso be used.

In response to receiving DL Trigger frame 44 that was broadcasted by AP24, each STA 28 processes the received Trigger frame to extractinformation required for generating a respective uplink PPDU 48.Specifically, STA 28 extracts user-specific information from therelevant User Info field (62). Note that each STA may have differentprocessing and storage capabilities, and therefore different STAs mayrequire different time-durations for processing the Trigger frame andgenerating the response PPDU. Moreover, considering the sequence of theUser Info fields 62 in MAC Trigger frame 52, the later a User Info fieldappears in the sequence, the less processing time remains for thecorresponding STA compared to the other STAs.

For simultaneous uplink response, all the STAs are required to completeprocessing the DL Trigger frame and produce the PPDU on time, e.g.,before uplink transmission of PPDUs 48 starts. In some embodiments, MACmodule 32 determines processing-time constraint 60, based on the longesttime requirement reported by the STAs participating in simultaneous ULtransmission, for meeting the processing-time requirements of all STAs.

The configurations of communication system 20 and AP 24 of FIG. 1 aregiven by way of example, and other communication system and APconfigurations can be used. Elements of the AP that are not mandatoryfor understanding the disclosed techniques have been omitted from thefigure for the sake of clarity.

In the example AP configuration shown in FIG. 1, MAC processor 32 andPHY processor 36 are implemented as separate Integrated Circuits (ICs).In alternative embodiments, however, the MAC processor and PHY processormay be integrated on separate semiconductor dies in a single Multi-ChipPackage (MCP) or System on Chip (SoC), (e.g., as part of BB processor30) and may be interconnected by an internal bus.

In some embodiments, some or all of the elements of AP 24, such as MACprocessor 32 and PHY processor 36 are implemented in hardware, such asusing one or more Field-Programmable Gate Arrays (FPGAs) orApplication-Specific Integrated Circuits (ASICs). In an alternativeembodiment, certain elements such as one or more of trigger frameconstructor 50, MAC padding module 64, ECC module 56 and OFDM module 58,are implemented in a programmable processor, which is programmed insoftware to carry out the functions described herein. The software maybe downloaded to the processor in electronic form, over a network, forexample, or it may, alternatively or additionally, be provided and/orstored on non-transitory tangible media, such as magnetic, optical, orelectronic memory.

The IEEE 802.11ax standard cited above specifies, e.g., in section27.5.3.2.3, a naïve padding scheme in which a time constraint denoted“MinTrigProcTime” can be configured to 0, 8 or 16 microseconds, orequivalently to 0, 2 or 4 OFDM symbols (assuming OFDM symbol duration offour microseconds). The naïve padding scheme is based on translating thevalue of MinTrigProcTime into number of padding bits by multiplying thecorresponding number of OFDM symbols by the number of bits per symbol.

As will be described in detail below, in terms of OFDM symbols to whichthe encoded bits are mapped, “B_SYM” denotes the OFDM symbol of the PPDUthat contains either (i) when a BCC scheme is used—the last encoded bitof the last User Info field (62), or (ii) when a LDPC scheme is used—thelast encoded bit of the LDPC code word that encodes the last bit of theUser info field. In the present context, the bits encoded using the BCCscheme are collectively considered as a single code word.

Unlike the naïve padding scheme, in the disclosed embodiments thepadding length is determined while taking into considerationmodifications to the encoding scheme caused by adding the padding bits,as explained herein. In the naïve padding scheme above, an assumption ismade that B_SYM can be determined directly from the number of payloadits to be encoded, prior to adding any padding bits. This assumption ishowever not always valid, e.g., when the underlying encoding schemedepends on the total number of payload bits to be encoded, including thepadding bits. For example, an encoding scheme that applies puncturingremoves some of the parity bits after encoding with an ECC, may resultin a different location of B_SYM in the sequence of OFDM symbolscompared to encoding without puncturing. As another example, in LDPCencoding into multiple code words, the code word length, the index ofthe code word that encodes the last bit of the last User Info field andB_SYM may depend on the total number of payload bits to be encoded,including padding bits whose number is not yet determined.

Padding schemes that improve over the naïve padding scheme above, willbe described in detail below.

FIGS. 2A and 2B are diagrams that schematically illustrates a partialpacket 70 comprising a Trigger frame 52, and corresponding encoded bits72 and OFDM symbols 74 resulting from encoding the partial packets usinga Binary Convolutional Code (BCC) or a Low-Density Parity-Check (LDPC)encoding scheme. Partial packets 70 may each be, for example, part of aPPDU comprising the MAC Trigger frame.

in FIG. 2A, partial packet 70A comprises a 16-bit SERVICE bits field 76,MAC Trigger frame 52 and a 6-bit TAIL field 78. Partial packet 70 isencoded using a BCC encoding scheme to produce BCC encoded bits 72A,which are mapped into OFDM symbols 74A. In some embodiments, the tasksof BCC encoding and mapping the encoded bits into the OFDM symbols arecarried out using ECC module 56 and OFDM module 58, respectively.

As shown in FIG. 2A, the last bit of the last User Info field 62 of MACTrigger frame 52 is mapped into an OFDM symbol 80A denoted B_SYM. Timeperiod DT 82 denotes the additional time required for meeting theprocessing-time constraint DT>MinTrigProcTime. In some embodiments, theoverall number of padding bits required for meeting the constraint maybe split into subgroups containing respective numbers “NP1” and “NP2” ofpadding bits. The NP1 padding bits are required for reaching the farboundary of B_SYM 80A, and the NP2 padding bits are required forincreasing the PPDU duration time by DT 82. The overall number ofpadding bits is given by the sum NPAD=NP1+NP2.

In FIG. 2B, partial packet 70B comprises a 16-bit SERVICE bits field 76and MAC Trigger frame 52. Partial packet 70B is encoded using a LDPCscheme to produce encoded bits in the form of one or more LDPC codewords 72B. The encoded bits of the LDPC code words are mapped into OFDMsymbols 74B. In some embodiments, the tasks of LDPC encoding and mappingthe encoded bits of the LDPC code words into the OFDM symbols arecarried out using FCC module 56 and OFDM module 58, respectively.

As shown in FIG. 2B, the last bit of the last User Info field 62 of MACTrigger frame 52 is encoded into the n^(th) LDPC code word 84, denotedCWn. The last bit of CWn is mapped into OFDM symbol B_SYM 80B. DT 82denotes the additional time required for meeting the processing-timeconstraint DT>MinTrigProcTime. In FIG. 2B, the overall number of paddingbits required for meeting the constraint may be split into threesubgroups as follows: “NP0” padding bits are required for reaching thefar boundary of CWn, “NP1” padding bits are required for reaching thefar boundary of B_SYM 80B, and “NP2” padding bits are required forincreasing the PPDU duration time by DT 82. The overall number ofpadding bits is given by the sum NPAD=NP0+NP1+NP2.

FIG. 3 is a flow chart that schematically illustrates a method forpadding a Trigger frame for meeting a processing-time constraint, inaccordance with an embodiment that is described herein. The method willbe describe as executed by MAC module 32 of AP 24 of FIG. 1.

In the method of FIG. 3, partial numbers of padding bits correspondingto three respective subgroups of the total number of padding bits aredenoted NP0, NP1 and NP2, as described above with reference to FIGS. 2Aand 2B. As shown in FIGS. 2A and 2B, NP0 (only in FIG. 2B) comprises thenumber of padding bits required for reaching the far boundary of arelevant LDPC code word, NP1 (in FIGS. 2A and 2B) comprises the numberof padding bits required for reaching the far boundary of B_SYM, and NP2(in FIGS. 2A and 2B) comprises the number of padding bits required forincreasing the PPDU time duration by MinTrigProcTime time units formeeting the processing-time constraint. The processing-time constraintMinTrigProcTime (whose value is common to STAs 28 participating in thesimultaneous UL transmission) is typically specified in suitable timeunits such as microseconds, for example. Alternatively, theprocessing-time constraint may be specified in other types of units, aswill be described further below.

The method begins with MAC module 32 determining processing-timeconstraint 60, at a time constraint setting operation 100. In someembodiments, before initiating a Trigger frame, AP 24 receives, fromeach of one or more STAs 28, a respective time requirement indicative ofthe processing time that STA requires for processing DL trigger frame44. Based on the time requirements received from multiple STAs, MACmodule 32 determines processing-time constraint 60, e.g., in accordancewith the longest time requirement requested the STAs, in an embodiment.

In some embodiments, the processing time required by a given STA dependson the location of its USER INFO filed 62 in the Trigger frame (52). Forexample, a STA whose USER INFO field appears later the Trigger frame hasless time for processing the Trigger frame including its own USER INFOfield, compared to other STAs whose USER INFO fields appear earlier inthe Trigger frame. In such embodiments, MAC module 32 determinesprocessing-time constraint 60 based on both the time requirementrequests received from the STAs, and the respective locations of theUSER INFO fields in the Trigger frame. In an embodiment, the MACprocessor is configured to adjust one or more of the time requirementrequests received from the STAs, based on the respective locations ofthe USER INFO fields of the STAs in the Trigger frame, and to select,for example, the longest among the adjusted time requirement requests.

At an encoding type query operation 104, MAC module 32 checks whetherECC module is configured to apply a BCC or LDPC encoding scheme. WhenECC module 56 is configured to a BCC scheme, the method proceeds tocalculate the number of padding bits for BCC, starting at operation 108.Otherwise, the method proceeds to calculate the number of padding itsfor LDPC, starting at operation 124.

At an NP1 (BCC) calculation operation 108, MAC padding module 64calculates NP1 for the BCC case. In the description and Equations givenbelow, the following notations may be used:

“N_DBPS” denotes the number of data bits per OFDM symbol.

“N_CBPS” denotes the number of coded bits per OFDM symbol.

“B_SYM” denotes the index of B_SYM 80A or 80B within the sequence ofOFDM symbols 74A or 74B.

“Nx” denotes the number payload bits of MAC Trigger frame 52 comprisedwithin the fields—Frame control up to and including the last User Infofield 62.

“Nsv” denotes the number of bits in SERVICE bits field 76. In the IEEE802.11 family, Nsv comprises 16 bits.

“Ntl” denotes the number of bits in TAIL field 78. In the IEEE 802.11family, Ntl comprises 6 bits.

For IEEE 802.11a/n packets, Non-High Throughput (Non-HT) and HT PPDUs,MAC padding module 64 calculates B_SYM as given by:B_SYM=ceil[(Nx+Nsv+Ntl)/N_DBPS]  Equation 1:and further calculates NP1 as:NP1=B_SYM·N_DBPS−(Nx+Nsv+Ntl)  Equation 2:

The “Ceil[ ]” operator in Equation 1 above (and in some Equations below)denotes a round-up operator to the nearest integer.

At an NP2 (BCC) calculation operation 112, the MAC padding modulecalculates NP2 as given by:NP2=ceil(MinTrigProcTime/T_SYM)·N_DBPS  Equation 3a:wherein T_SYM denotes the OFDM symbol time duration (e.g., specified inmicroseconds). In Equation 3a, in accordance with the IEEE 802.11axstandard, T_SYM is assumed to be, e.g., 16 microseconds. Alternatively,e.g., in the IEEE 802.11a/n/ac standard, T_SYM is 4 microseconds, andNP2 is defined in terms of four-microsecond symbols, and calculated as:NP2=ceil(MinTrigProcTime/4)·N_DBPS  Equation 3b:

Further alternatively, MAC padding module 64 may calculate NP2 using theNaïve padding scheme specified in the IEEE 802.11ax standard mentionedabove.

At a BCC padding bits calculation operation 116, MAC padding module 64calculates the total number of padding bits NPAD (rounded up to bytes)for the BCC case as given by:NPAD=8·ceil[(NP1+NP2)/8]  Equation 4:

In some embodiments, e.g., when using PPDUs in accordance with the IEEE802.11ac Very High Throughput (VHT) or the IEEE 802.11ax High Efficiency(HE) standards, the encoding flow comprises a phase of padding to thesubsequent OFDM symbol (or OFDM segment in case of IEEE 802.11axstandard). In such embodiments, the calculation of NP1 above may beomitted, and the index of B_SYM and the pre-FEC padding factor (alsodenoted a_factor) are calculated by the physical layer based on the MPDUreceived. The number NP2 of padding bits is calculated by the MACpadding module as given above, e.g., in Equation 3a.

At a padding operation 120, trigger frame constructor 50 receives theoverall number of padding bits NPAD from MAC padding module 64, and whenNPAD>0 inserts NPAD padding bits into Padding field 66 of MAC Triggerframe 52. Trigger frame constructor 50 may insert the padding bits usingany suitable method. In one embodiment, the trigger frame constructorinserts the padding bits by positioning the FCS field after a gap ofNPAD bits relative to the last bit of User Info field 62. In someembodiments, the trigger frame constructor may set the binary values ofthe padding bits randomly or to predefined bit values. Alternatively,the trigger frame constructor leaves the NPAD padding bits withundetermined bit values.

As noted above, when at operation 104 the ECC module is configured toapply a LDPC scheme, the method proceeds to a NP0 calculation operation124. At operation 124, MAC padding module 64 calculates NP0 for reachingthe far boundary of a LDPC code word 84 whose last encoded bit is mappedinto B_SYM 80B. In some embodiments, the MAC padding module calculatesNP0 as:NP0=ceil[(Nx+Nsrv)/(L _(LDPC) ·R)]·(L _(LDPC) ·R)−(Nx+Nsrv)  Equation 5:

In Equation 5, L_(LDPC) denotes the length (in bits) of the LDPC codewords, R denotes the rate of the LDPC code used, and (L_(LDPC)·R)comprises the number of message bits in the LDPC code word.

In some embodiments, e.g., when processing PPDUs in accordance with theIEEE 802.11n/ac/ax standards, the LDPC code word length L_(LDPC) usedwithin the LDPC encoding flow depends on the total number of payloadbits, including the padding bits. This may cause a problem, because MAClayer padding, e.g., as given in Equation 5, is based on L_(LDPC), whichdepends on the number of padding bits that is not yet determined.

In one embodiment, to overcome this problem, the MAC padding modulecalculates NP0 using Equation 5 in which the L_(LDPC) is selected to themaximum value supported, e.g., L_(LDPC)=1944 bits. In anotherembodiment, the MAC padding module selects a L_(LDPC) value smaller thanthe maximum value supported, e.g., when the LDPC code word length isexpected to remain unchanged after including the padding bits. This maybe relevant for short frames (small Nx value) and/or when using smallMCSs.

At an NP1 (LDPC) calculation operation 128, MAC padding module 64calculates NP1 for the LDPC case. Let an intermediate number of bits,denoted Nb, be given by:Nb=ceil[(Nx+Nsrv)/(L _(LDPC) ·R)]·(L _(LDPC) ·R)  Equation 6:

For packets formatted in accordance with the IEEE 802.11n/ac standards,the MAC padding module calculates B_SYM 80B as:B_SYM=ceil[Nb/N_DBPS]  Equation 7:and calculates NP1 as given by:NP1=B_SYM·N_DBPS−Nb  Equation 8:

For packets formatted in accordance with the IEEE 802.11ax standard, NP1is required for padding up to the subsequent OFDM segment, which isgiven as part of the encoding flow.

In some embodiments, instead of calculating NP0 and NP1 separately, MACpadding module 64 calculates the sum of NP0 and NP1 as given by:NP01=ceil[Nb/Nbs]·Nbs−Nb  Equation 9:wherein Nbs is given by:Nbs=(N_DPBS·L _(LDPC) ·R)  Equation 10:

At a LDPC NP2 calculation operation 132, the MAC padding modulecalculates NP2, for example, using the expression given in Equation 3aabove.

At a LDPC padding bits calculation operation 136, the MAC padding modulecalculates the total number of padding bits NPAD (rounded up to bytes)for the LDPC case as given by:NPAD=8·ceil[(NP0+NP1+NP2)/8]  Equation 11:

The method then proceed to operation 120 to insert NPAD padding bits toPadding field 66, as described above. Following operation 120, themethod terminates.

In some embodiments, the encoding scheme applied using FCC module 56includes puncturing, shortening or both, which reduces the length of thecode word. In puncturing, some of the code word bits are nottransmitted. In shortening, ‘0’ bits are inserted in place of some databits, and these bits are not transmitted. As a result ofpuncturing/shortening, the last symbol B_SYM, which contains the lastuser info field, may now be (B_(SYM)+1), hence the effective duration ofthe processing time required with respect to (B_(SYM)+1) is reduced,which may result in violating the processing-time constraint. In someembodiments, to prevent such a violation, the MAC padding module insertsadditional padding bits to Padding field 66, for example, a number ofadditional padding bits corresponding to a time duration of one or moreOFDM symbols.

In some embodiments, the number of puncturing/shortening bits and theLDPC code word length depend on the total number of payload bits, andtherefore may change as a result of adding padding bits. For example,adding the padding bits may increase the number of shortening bits usedduring encoding, which may violate the processing-time constraint.

Let NP3 denote the number of padding bits required in addition to theNP0, NP1 and NP2 padding bits above. Let Ncw=Ncw0+1, wherein Ncw0denotes the number of LDPC code words prior to adding the padding bits.In order to meet the processing-time constraint, the expression belowshould be satisfied:

$\begin{matrix}{{{L_{LDPC} \cdot R} - \frac{{L_{LDPC} \cdot R} - ( {{{NP}\; 1} + {{NP}\; 2} + {{MP}\; 3}} )}{Ncw}} < ( {{{NP}\; 0} + {{NP}\; 1} + {{NP}\; 2} + {{NP}\; 3}} )} & {{Equation}\mspace{14mu} 12}\end{matrix}$

In Equation 12, L_(LDPC) denotes the LDPC code word length before addingthe padding bits.

In some embodiments, based on Equation 12, the MAC padding modulecalculates NP3 using the expression:

$\begin{matrix}{{{NP}\; 3} > {{L_{LDPC} \cdot R} - \frac{{NP}\; 0}{( {1 - \frac{1}{Ncw}} )} - ( {{{NP}\; 1} + {{NP}\; 2}} )}} & {{Equation}\mspace{14mu} 13}\end{matrix}$

In these embodiments, the MAC padding module calculates NPAD atoperation 136 above, as:NPAD=NP0+NP1+NP2+NP3  Equation 14:

In some embodiments, AP 24 is configured to operate in a Space-TimeBlock Coding (STBC) mode. In the STBC mode, AP 24 transmits multiplecopies of a data stream via multiple antennas 42. In such embodiments,MAC padding module 64 calculates the partial numbers of padding bitsNP0, NP1, NP2 and/or NP3 while taking into consideration whether the APoperates in the STBC mode, or not. Let STBCon=0/1 denote respectiveoff/on configurations of the STBC mode. Equations for calculating NP0,NP1, NP2 and NP3 assuming a 16-bit SERVICE bits field are given herein:

$\begin{matrix}{\mspace{79mu}{N^{\prime} = {{N\_ DBPS} \cdot ( {{STBCon} + 1} )}}} & {{Equation}\mspace{14mu} 15} \\{\mspace{79mu}{{{NP}\; 0} = {{{{ceil}\lbrack \frac{( {{Nx} + 16} )}{( {L_{LDPC} \cdot R} )} \rbrack} \cdot ( {L_{LDPC} \cdot R} )} - ( {{Nx} + 16} )}}} & \; \\{\mspace{79mu}{{{NP}\; 1} = {{{{ceil}\lbrack \frac{{NP}\; 0}{N^{\prime}} \rbrack} \cdot N^{\prime}} - {{NP}\; 0}}}} & \; \\{\mspace{79mu}{{{NP}\; 2} = {\lbrack {{{ceil}( \frac{MinTrigProcTime}{T\_ SYM} )} + 1} \rbrack \cdot {N\_ DBPS}}}} & \; \\{{{NP}\; 3} = {\max\{ {0,{{{ceil}\lbrack \frac{{L_{LDPC} \cdot R} - \frac{{NP}\; 0}{( {1 - \frac{1}{Ncw}} )} - ( {{{NP}\; 1} + {{NP}\; 2}} )}{N^{\prime}} \rbrack} \cdot N^{\prime}}} \}}} & \;\end{matrix}$

In the example of Equation 15 above, the calculation of NP2 includesextra padding bits corresponding to one additional OFDM symbol, comparedto Equation 3a above. In some embodiments, for increasing the likelihoodof meeting the processing-time constraint, MAC padding module 64calculates the expressions in Equation 15 using the maximum code wordlength supported, e.g., L_(LDPC)=1944 bits.

Note that the ceil[·] operation in calculating NP2 may result in anadditional LDPC codeword, which may affect the LDPC encoding flow,thereby possibly violating the processing-time constraint, as explainedabove. In some embodiments, to reduce the probability of violating theprocessing-time constraint, the MAC padding module increases NP2 by anumber of bits corresponding to two OFDM symbols (instead of one OFDMsymbol in Equation 15). The inventors discovered, using computersimulations, that even when inserting additional padding bitscorresponding to two OFDM symbols, in certain modulation schemes such asMCS 10/11, violation of the processing-time constraint may occur. Insome embodiments, when using these modulation schemes, the MAC paddingmodule calculates NP2 by adding a number of padding bits correspondingto a number of three OFDM symbols.

In some embodiments, MAC padding module 64, selects one or more methodsamong the methods described above for calculating NP0 . . . NP3, basedon parameters such as the length of the MAC Trigger frame, the MCS usedand the like. Moreover, in some embodiments, the MAC module calculatesNPAD by summing only part of the partial numbers of padding bits NP0 . .. NP3. For example, for meeting a processing-time constraint of 8microseconds, or 16 microseconds with 80 MHz or 160 MHz channels, NPADmay be calculated as NPAD=NP0+NP2+NP3, i.e., omitting the calculation ofNP1. In this embodiment, the calculation of NP2, e.g., using Equation 15above, is modified to increase the number of padding bits by a number ofbits corresponding to two OFDM symbols in case of 8 microsecondsconstraint and to three OFDM symbols in case of 16 microsecondsconstraint. In case of a 16 microseconds constraint and 20 MHz or 40 MHzchannels, NPAD may be calculated as NPAD=NP0+NP1+NP2+NP3, wherein NP2 isextended by a number of padding bits corresponding to three OFDMsymbols. In some embodiments, the MAC padding module adds a number ofpadding bits corresponding to three OFDM symbols for all cases, whichsimplifies the calculations above, but reduces the efficiency in usingthe available bandwidth. In some embodiments, when the bandwidth isconfigured to 80 MHz or to 160 MHz, the NP1 bits may be excluded.

The methods described above may result in a large overhead in terms ofthe additional number of padding bits corresponding to one or more OFDMsymbols. Next an alternative method is described, for accuratelydetermining the number of padding bits required for meeting theprocessing-time constraint. This alternative method will be described asexecuted by MAC padding module 64 as a series of operations.

In some embodiments, MAC padding module 64 sets an initial length valuegiven by N_pld_init=Nx+16, and calculates a partial number of paddingbits denoted N1 as:

$\begin{matrix}{{N\; 1} = {{N^{\prime} \cdot {{ceil}( \frac{{N\_ pld}{\_ init}}{N^{\prime}} )}} - {{N\_ pld}{\_ init}}}} & {{Equation}\mspace{14mu} 16}\end{matrix}$wherein N′=N_DBPS·(STBCon+1). The MAC padding module calculates apartial number of padding bits N2 as given by:

$\begin{matrix}{{N\; 2} = {\lbrack {{ceil}( \frac{MinTrigProcTime}{T\_ SYM} )} \rbrack \cdot {N\_ DBPS}}} & {{Equation}\mspace{14mu} 17}\end{matrix}$and calculates N_pld as:N_pld=N_pld_init+N1+N2

The MAC padding module calculates an initial number of symbols Nsym_initand an initial number of available bits given by:

$\begin{matrix}{{Nsym\_ init} = {( {STBC}_{ON} ) \cdot {{ceil}( \frac{N\_ pld}{N^{\prime}} )}}} & {{Equation}\mspace{14mu} 19} \\{{Navbits\_ init} = {{N\_ CBPS} \cdot {Nsym\_ init}}} & \;\end{matrix}$wherein N_CBPS denotes the number of coded bits per OFDM symbol. The MACpadding module calculates the number N_CW of LDPC code words and thecode word length L_(LDPC) as specified, for example, in section19.3.11.7.5—LDPC PPDU encoding process, in “Part 11: Wireless LAN MediumAccess Control (MAC) and Physical Layer (PHY) Specifications, IEEE Std802.11™-2016,” (A revision of IEEE Std 802.11-2012), and calculates thenumber of LDPC code words occupied the Padding field as:

$\begin{matrix}{{ncw\_ cond} = {{ceil}\lbrack {( {{{ceil}( \frac{MinTrigProcTime}{T\_ SYM} )} + 1} ) \cdot \frac{N\_ CBPS}{L_{LDPC}}} \rbrack}} & {{Equation}\mspace{14mu} 20}\end{matrix}$

The MAC module calculates:Ncw′=(ncw_cond−N_CW+N_CW_nopad)

The parameter N_CW_nopad in Equation 21 denotes the number of LDPC codewords assuming no pre-FEC padding, and payload length of N_pld_initbits.

The MAC padding module checks whether the condition 0<Ncw′ is true, andif so, calculates a partial number of padding bits N3 as:

$\begin{matrix}{{N\; 3} = {{L_{LDPC} \cdot R \cdot {\max( {0,{{Ncw}^{\prime} - 1}} )}} + {{{ceil}( \frac{N\_ pld}{L_{LDPC} \cdot R} )} \cdot L_{LDPC} \cdot R} - {N\_ pld} + 1}} & {{Equation}\mspace{14mu} 22}\end{matrix}$

The MAC padding module updates the following variables:N_CW=N_CW_nopad+ncw_cond, N_pld=N_pld+N3 and overflow=1.

When the condition 0<Ncw′ above is false, the MAC padding module setsN3=0 and calculates the overflow parameter as given by:

$\begin{matrix}{{overflow} = {{N\_ pld} - \lbrack {{floor}\;{( \frac{N\_ pld}{L_{LDPC} \cdot R} ) \cdot L_{LDPC} \cdot R}} \rbrack}} & {{Equation}\mspace{14mu} 23}\end{matrix}$

In an embodiment, N_CW and L_(LDPC) satisfy: N_CW=1 and L_(LDPC)≤1296,in which case the MAC adding module sets L_(LDPC)=1296. Since thecombination of L_(LDPC)=648 and N_CW=2 is invalid, the MAC paddingmodule calculates overflow and N3 as:N3=1944·R−N_pld+1overflow=max[0.1944·R−N_pld−N3+1]  Equation 24:

In Equations 23 and 24, N_CW_nopad is omitted.

Next, the MAC padding module calculates another partial number ofpadding bits denoted N4, for ensuring that the initial payloadN_pld_init does not overflow into the subsequent code word(N_CW_nopad+1) as a result of padding, encoding and applying shortening,puncturing or both. The condition is formulated as:

$\begin{matrix}{{{ncw\_ cond} \cdot ( {{L_{LDPC} \cdot R} - \frac{{L_{LDPC} \cdot R} - {overflow} - {N\; 4}}{N\_ CW}} )} < {{N\; 1} + {N\; 2} + {N\; 3} + {N\; 4}}} & {{Equation}\mspace{14mu} 25}\end{matrix}$and MAC padding module calculates N4 accordingly as given by:

$\begin{matrix}{{N\; 4^{\prime}} = \frac{\begin{matrix}{{{ncw\_ cond} \cdot L_{LDPC} \cdot R \cdot ( {1 - \frac{1}{N\_ CW}} )} +} \\{( \frac{{ncw\_ cond} \cdot {oveflow}}{N\_ CW} ) - {N\; 1} + {N\; 2} + {N\; 3}}\end{matrix}}{( {1 - \frac{ncw\_ cond}{N\_ CW}} )}} & {{Equation}\mspace{14mu} 26} \\{{N\; 4} = {\max\lbrack {0,( {{N\; 4^{\prime}} + {N\_ CW}} )} \rbrack}} & {{Equation}\mspace{14mu} 27}\end{matrix}$

The additional N_CW bits in Equation 27 are required in cases in whichthe number of shortening bits is not an integral multiple of N_CW. Thetotal number of padding bits is given by NPAD=N1+N2+N3+N4. The MACpadding module updates the overall payload length:N_pld=N_pld+N4  Equation 28:

The alternative method described above may violate the processing-timeconstraint for a 20 MHz channel, MCS0 constellation, Nss7 (Seven spatialstreams are multiplexed and transmitted in the Trigger frame,MinTrigProcTime=16 microseconds, and N_pld_init is between 1 and 20bytes. In this case, the MAC padding module calculates N2 using theexpression:

$\begin{matrix}{{N\; 2} = {{N\_ DBPS} \cdot \lbrack {{{ceil}( \frac{MinTrigProcTime}{T\_ SYM} )} + 1} \rbrack}} & {{Equation}\mspace{14mu} 29}\end{matrix}$

Another padding method is described herein. The method is conservativein the sense that it adds padding bits corresponding to a number of twoextra OFDM symbols.

The method begins with MAC padding module 64 calculating B_SYM based onthe current value of N_pld (Nx+16), and calculates the number of codewords N_CW based on the current value of N_pld and on the calculatedvalue of B_SYM. For example, the MAC padding module calculatesB_SYM=ceil[N_pld/N_DBPS]·N_DBPS. The MAC padding module then calculatesfirst padding length denoted Npd1 that includes padding corresponding totwo extra OFDM symbols given by.Npd1=ceil(MinTrigProcTime/T_SYM+2)·N_DBPS  Equation 30:

The MAC padding module calculates an updated payload length given by:N_pld′=Nx+16+Npd1  Equation 31:and calculates an updated value B_SYM′ based on N_pld′, and calculatesan updated value N_CW′ based on N_pld′ and B_SYM′.

The MAC padding module initializes a second padding length denoted Npd2to a zero value Npd2=0, and possibly modifies Npd2 depending on whetherthe processing-time constraint comprises 8 or 16 microseconds asfollows:For MinTrigProcTime=8:if(N_CW′−N_CW<2,Npd2=1944·R)For MinTrigProcTime=16:if(N_CW′−N_CW<3,Npd2=2916·R)  Equation 32:

The MAC padding module calculates the overall number of padding bits as:NPAD=Npd1+Npd2  Equation 33:

Next, we describe a method that calculates the required number ofpadding bits using an iterative process. The iterative process presentsa tradeoff between accuracy and convergence time. Searching for therequired number of padding bits at high-resolution (up to a single bitresolution) will typically require a higher number of iterations, andvice versa.

FIG. 4 is a flow chart that schematically illustrates a method foriteratively determining the padding length required in a Trigger framefor meeting a processing-time constraint, in accordance with anembodiment that is described herein.

The method begins with MAC padding module 64 determining processing-timeconstraint 60, at a time constraint setting operation 200. Operation 200essentially similar to operation 100 described above with reference toFIG. 3.

At an initialization operation 204, the MAC padding module initializesvarious parameters: an iteration index i=1, the number of padding bitsNPAD=0, and an initial payload length Npld(i)=Nx+16.

At a symbol location calculation operation 208, the MAC padding modulecalculates the index B_SYM(i) of OFDM symbol B_SYM (e.g., 80B) for thei^(th) iteration, based on the current payload length Npld(i). Forexample, the MAC padding module calculates:B_SYM(i)=ceil[Npld(i)/N_DBPS]·N_DBPS.  Equation 34:

At a duration calculation operation 212, the MAC padding modulecalculates a time duration denoted Td(i) between the the PPDU startpoint and the time point corresponding to the far boundary of B_SYM. Ata time-constraint checking operation 216, the MAC padding module checkswhether the processing-time constraint is met, and if not, proceeds to apadding operation 220. At operation 220, the MAC padding module acids toNPAD number NPAD(i)>0 of padding bits, i.e., NPAD=NPAD+NPAD(i). The MACpadding module may select any suitable number of padding bits NPAD(i) tobe added in the i^(th) iteration. Typically, by adding large numbers ofpadding bits in the iterations, the time-constraint may be met with asmall number of iterations. In one embodiment, the MAC padding moduleadds the same number of padding bits each of the iterations. In anotherembodiment, the MAC module may add different numbers of padding bits indifferent iterations. In an example embodiment, the MAC padding moduleadds a number of padding bits given byNPAD(1)=ceil(MinTrigProcTime/T_SYM)·N_DBPS when the condition inoperation 216 is true in the first iteration.

At a payload updating operation 224, MAC padding module 64 updates thepayload length by calculating Npld(i+1)=Npld(i)+NAPD(i). At an iterationupdate operation 228, the MAC padding module updates the iteration indexi=i+1, and loops back to operation 208 to re-calculate the index of theB_SYM based on the updated payload length.

When the condition at operation 216 is false, the MAC padding moduleproceeds to a rounding operation 232, at which the MAC padding modulerounds the number padding bits NPAD up to bytes, e.g., by calculatingNPAD=ceil(NPAD/8)·8, wherein NPAD was accumulated at operation 220 overone or more iterations.

At a padding insertion operation 236, the MAC padding module inserts the(rounded up to bytes) number of bits NPAD of operation 232 into Paddingfield 66 of MAC Trigger frame 52. Following operation 236, the methodterminates.

In the embodiments described above, the processing-time constraint istypically defined in time units such as microseconds. For example, asspecified in the IEEE 802.11ax standard, the processing-time constrainthas three possible Values, 0, 8 or 16 microseconds. Alternatively, theprocessing-time constraint may be specified in units of the OFDM symbolduration. For example, in the IEEE 802.11a/n/ac standards, theprocessing-time constraint may refer to the time duration of 0, 2 or 4OFDM symbols. In the IEEE 802.ax standard, the processing-timeconstraint may be provided as zero or one “long” OFDM symbol, oradditional padding bits for covering two “short” OFDM segments(increasing the pre-FEC padding factor, a-factor, by 2). In embodimentsin which the processing-time constraint is specified in units of OFDMsymbols (and/or OFDM segments) denoted MinTrigProcNumSym, the MACpadding module calculates the corresponding partial number of paddingbits required as N_DBPS·(MinTrigProcNumSym). Alternatively, the MACpadding calculates N_DBPS·(MinTrigProcNumSym+B), wherein B>0 denotes anumber of additional OFDM symbols required in case of encoding withpuncturing and/or shortening, e.g., set B as B=2.

In yet other embodiments, the processing-time constraint may bespecified directly in terms of the number of padding bits required.

In some embodiments, to ensure sufficient padding for meeting theprocessing-time constraint, the MAC module supports such padding onlyfor cases in which ECC module 56 is configured to use the BCC scheme.

The embodiments described above are given by way of example, and othersuitable embodiments can also be used. For example, the embodimentsabove are applicable not only to the Trigger frame specified in the IEEE802.11ax standard, but to other types of frames that include avariable-length padding field. As an example, the embodiments describedabove are applicable to frames containing a Triggered ResponseScheduling (TRS) Control subfield.

It is noted that the embodiments described above are cited by way ofexample, and that the present invention is not limited to what has beenparticularly shown and described hereinabove. Rather, the scope of thepresent invention includes both combinations and sub-combinations of thevarious features described hereinabove, as well as variations andmodifications thereof which would occur to persons skilled in the artupon reading the foregoing description and which are not disclosed inthe prior art. Documents incorporated by reference in the present patentapplication are to be considered an integral part of the applicationexcept that to the extent any terms are defined in these incorporateddocuments in a manner that conflicts with the definitions madeexplicitly or implicitly in the present specification, only thedefinitions in the present specification should be considered.

The invention claimed is:
 1. A Wireless Local-Area Network (WLAN) AccessPoint (AP), comprising: a Medium Access Control (MAC) processor,configured to: generate a trigger frame comprising at least (i) one ormore user information fields destined to one or more respective WLANclient stations (STAs), and (ii) a padding field comprising one or morepadding bits; determine a number of padding bits required that, afterbeing inserted into the padding field and the trigger frame beingencoded for transmission, satisfy a processing-time constraint imposedby the STAs; and insert the determined number of padding bits requiredin the padding field; and a physical layer (PHY) processor, configuredto: generate a packet from the trigger frame, including encoding thetrigger frame containing the padding field in accordance with an ErrorCorrection Code (ECC), into one or more Code Words (CWs) having a CWlength that depends on a number of padding bits in the padding field,wherein the PHY processor is configured to encode the trigger frame withthe ECC by applying a Low-Density Parity-Check (LDPC) code; generatemultiple modulated symbols from the one or more CWs of the packet; andtransmit the modulated symbols to the STAs; wherein the MAC processor isconfigured to determine the number of padding bits required based oncalculating a first partial number of padding bits required for reachingan end of a CW which encodes a last user information field of thetrigger frame; calculating a second partial number of padding bitsrequired for reaching a far boundary of a symbol to which the lastencoded bit of the CW that encodes a last user information field ismapped but not reaching the processing time constraint; calculating athird partial number of padding bits required for reaching theprocessing time constraint after the far boundary of the symbol to whichthe last encoded bit of the CW that encodes the last user informationfield is mapped; and summing the first partial number, second partialnumber, and the third partial number to determine the number of paddingbits which reaches the processing constraint; wherein the first partialnumber of padding bits, the second partial number of padding bits andthe third partial number of padding bits are calculated based onpuncturing performed during the LDPC encoding of the trigger frame. 2.The AP according to claim 1, wherein the MAC processor is configured toreceive, before generating the trigger frame, multiple processing-timeconstraint values from one or more respective STAs that participate in asimultaneous uplink transmission to be triggered by the trigger frame,and to determine the number of padding bits required based on a longestvalue among the multiple received processing-time constraint values. 3.The AP according to claim 2, wherein the MAC processor is configured toadjust one or more of the received processing-time constraint values,before selecting the longest value, based on respective locations of theuser information fields of the STAs in the Trigger frame.
 4. The APaccording to claim 1, wherein the MAC processor is configured todetermine the number of padding bits required, by evaluating an expectedmodification to an encoding scheme applied using the ECC caused byadding the padding bits, wherein the modification changes a length ofthe trigger frame.
 5. The AP according to claim 1, wherein theprocessing-time constraint is indicative of an additional processingtime required by a STA, wherein the MAC processor is configured todetermine the first partial number and the second partial number of thepadding bits required, independently of the processing-time constraint.6. The AP according to claim 1, wherein the MAC processor is configuredto determine the number of padding bits required using an iterativeprocess that iteratively increases the number of padding bits requireduntil the processing-time constraint is met.
 7. The AP according toclaim 1, wherein the AP supports a Space-Time Block Coding (STBC) modeof operation, and wherein the MAC processor is configured to determinethe number of padding bits required depending on the STBC mode.
 8. Amethod for communication, comprising: in a Wireless Local-Area Network(WLAN) Access Point (AP) that comprises a Medium Access Control (MAC)processor, and a physical layer (PHY) processor, generating by the MACprocessor a trigger frame comprising at least (i) one or more userinformation fields destined to one or more respective WLAN clientstations (STAs) and (ii) a padding field comprising one or more paddingbits; determining by the MAC processor a number of padding bits requiredthat, after being inserted into the padding field and the trigger framebeing encoded for transmission, satisfy a processing-time constraintimposed by the STAs, and inserting the determined number of padding bitsrequired in the padding field; generating a packet from the triggerframe, by the PHY processor, including encoding the trigger framecontaining the padding field in accordance with an Error Correction Code(ECC), into one or more Code Words (CWs) having a CW length that dependson a number of padding bits in the padding field, wherein the PHYprocessor is configured to encode the trigger frame with the ECC byapplying a Low-Density Parity-Check (LDPC) code; generating by the PHYprocessor multiple modulated symbols from the one or more CWs of thepacket; and transmitting the modulated symbols to the STAs, wherein theMAC processor is configured to determine the number of padding bitsrequired based on calculating a first partial number of padding bitsrequired for reaching an end of a CW which encodes a last userinformation field of the trigger frame; calculating a second partialnumber of padding bits required for reaching a far boundary of a symbolto which the last encoded bit of the CW that encodes a last userinformation field are mapped but not reaching the processing timeconstraint; calculating a third partial number of padding bits requiredfor reaching the processing time constraint after the far boundary ofthe symbol to which the last encoded bit of the CW that encodes the lastuser information field is mapped; and summing the first partial number,second partial number, and the third partial number to determine thenumber of padding bits which reaches the processing constraint; whereinthe first partial number of padding bits, the second partial number ofpadding bits and the third partial number of padding bits are calculatedbased on puncturing performed during the LDPC encoding of the triggerframe.
 9. The method according to claim 8, and comprising receiving bythe MAC processor, before generating the trigger frame, multipleprocessing-time constraint values from one or more respective STAs thatparticipate in a simultaneous uplink transmission to be triggered by thetrigger frame, and determining the number of padding bits required basedon a longest value among the multiple received processing-timeconstraint values.
 10. The method to claim 9, wherein each of the STAshas a respective user information field in the Trigger frame, andcomprising, adjusting one or more of the received processing-timeconstraint values, before selecting the longest value, based onrespective locations of the user information fields of the STAs in theTrigger frame.
 11. The method according to claim 8, wherein determiningthe number of padding bits required, comprises evaluating an expectedmodification to an encoding scheme applied using the ECC caused byadding the padding bits, wherein the modification changes a length ofthe trigger frame.
 12. The method according to claim 8, wherein theprocessing-time constraint is indicative of an additional processingtime required by a STA, wherein determining the number of padding bitsrequired comprises determining the first partial number and the secondpartial number of the padding bits required, independently of theprocessing-time constraint.
 13. The method according to claim 8, whereindetermining the number of padding bits required comprises performing aniterative process that iteratively increases the number of padding bitsrequired until the processing-time constraint is met.
 14. The methodaccording to claim 8, wherein the AP supports a Space-Time Block Coding(STBC) mode of operation, and wherein determining the number of paddingbits required comprises determining the number of padding bits requireddepending on the STBC mode.